1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a liquid crystal display and a fabricating method thereof that are capable of realizing a high aperture ratio as well as implementing a high-density storage capacitor.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls the light transmissivity of a liquid crystal cell in response to a video signal to display a picture. An active matrix LCD having a switching device for each liquid crystal cell is suitable for displaying a moving picture. The active matrix LCD mainly uses a thin film transistor (TFT) as the switching device. Since such an active matrix LCD can be made into a smaller device in size than the existent Brown tube or Cathrode Ray Tube (CRT), it has been widely used for a personal computer or a notebook computer as well as office automation equipment such as a copy machine, and portable equipment such as a cellular phone and a pager.
Referring to FIG. 1 and FIG. 2, the conventional LCD includes a gate line 2 and a data line 4 formed on a substrate 1 to cross each other, a TFT arranged at an intersection between a data line 4 and a gate line 2, and a storage capacitor overlapping with the gate line 2.
The gate line 2 and the data line 4 are electrically isolated from each other by a gate insulating film 9. Each pixel is driven by the TFT and electrically connected to the gate line 2 and the data line 4.
The TFT includes a gate electrode 54, a source electrode 51, a drain electrode 52, an active layer 5 and an ohmic contact layer 10. The gate electrode 54 is connected to the gate line 2. The gate insulating film 9 is entirely deposited onto the substrate 1 to cover the gate electrode 54 and the gate line 2. The active layer 5 and the ohmic contact layer 10 are formed on the gate insulating film 9 to overlap with the gate electrode 54. The source electrode 51 is connected to the data line 4 while the drain electrode 52 is opposed to the source electrode 51 having a desired channel size therebetween.
A protective layer 53 is entirely deposited onto the gate insulating film 9 to cover the gate line 2, the data line 4 and the TFT. A pixel electrode 55a is connected to the drain electrode 52 via a first contact hole 8, and is provided on the protective layer 53.
The storage capacitor is charged by a voltage on the previous gate line 2 upon scanning of the previous scanning line to apply the charged voltage to the pixel electrode 55a upon scanning of the following scanning line. The storage capacitor includes the gate line 2 and a storage electrode 6 opposed to each other having the gate insulating film 9 therebetween. The storage electrode 6 is connected to a transparent electrode pattern 55b via a second contact hole 18 defined on the protective layer 53. The transparent electrode pattern 55b is patterned simultaneously with the pixel electrode 55a. 
FIG. 3A to FIG. 3E are sectional views for explaining a method of fabricating the LCD device shown in FIG. 2.
Referring first to FIG. 3A, the gate electrode 54 and the gate line 2 are provided on the substrate 1. The gate electrode 54 and the gate line 2 are formed by entirely depositing a metal such as aluminum (Al) or copper (Cu), etc. onto the substrate 1 and then patterning it.
Referring to FIG. 3B, the active layer 5 and the ohmic contact layer 10 are provided on the gate insulating film 9.
The gate insulating film 9 is formed by depositing an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) and then patterning it. The active layer 5 is formed from amorphous silicon that is not doped with an impurity. In contrast, the ohmic contact layer 10 is formed from amorphous silicon doped with an n-type or p-type impurity at a high concentration.
The active layer 5 and the ohmic contact layer 10 are formed by depositing first and second semiconductor material layers after forming the gate insulating film 9 on the substrate 1 to cover the gate electrode 54 and then patterning them.
Referring to FIG. 3C, the data line 4 (not shown), the storage electrode 6, the source electrode 51 and drain electrode 52 are provided on the gate insulating film 9. The source electrode 51 and drain electrode 52 are formed by entirely depositing a metal layer such as chromium (Cr) or molybdenum (Mo) using a chemical vapor deposition (CVD) technique or a sputtering technique and then patterning it. After the source electrode 51 and drain electrode 52 were patterned, the ohmic contact layer 10 is formed at an area corresponding to the gate electrode 54 and is also patterned to expose the active layer 5. A portion of the active layer 5 exposed by the source electrode 51 and drain electrode 52 serves as a channel. The data line 4 (not shown), the storage electrode 6, the source electrode 51 and drain electrode 52 are made from a metal such as chromium (Cr) or molybdenum (Mo).
Referring to FIG. 3D, the protective layer 53 and the first contact hole 8 and second contact hole 18 are provided on the gate insulating film 9.
The protective layer 53 and the first contact hole 8 and second contact hole 18 are formed by depositing an insulating material on the gate insulating film 9 to cover the source electrode 51 and drain electrode 52 and then patterning it. The protective layer 53 is made from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material having a small dielectric constant such as an acrylic organic compound, Teflon, benzocyclobutene (BCB), Cytop or perfluorocyclobutane (PFCB).
The protective layer 53 is provided with the first contact hole 8 and second contact hole 18. The first contact hole 8 is defined to pass through the protective layer 53, to thereby expose a portion of the surface of the drain electrode 52. Similarly, the second contact hole 18 is defined to pass through the protective layer 53, to thereby expose a portion of the surface of the storage electrode 6.
Referring to FIG. 3E, the pixel electrode 55a is provided on the protective layer 53. The pixel electrode 55a is formed by depositing a transparent conductive material such as indium-tin-oxide (ITO), indium-zinc-oxide (IZO) or indium-tin-zinc-oxide (ITZO) on the protective layer 53 and then patterning it. The pixel electrode 55a is electrically connected, via the first contact hole 8, to the drain electrode 52, and is electrically connected, via the second contact hole 18, to the storage electrode 6.
In such an LCD, the storage electrode 6 should have a sufficiently large capacitance value so that it can reduce variation in a data voltage charged in the pixel electrode 55a. Although the storage electrode 6 is extended into a pixel area to increase its capacitance value, the pixel area is narrowed by the extension of the storage electrode 6 into the pixel area, thus reducing aperture ratio. Moreover, since black matrices provided on the upper glass substrate to protect light leakage between the pixels overlap with the pixel area by approximately 5 μm at the left/right end and the upper/lower end of the pixel electrode 55a,the pixel area is reduced by the overlap and, hence, aperture ratio is reduced.
FIG. 4 represents an equivalent circuit of a pixel cell in the LCD.
In FIG. 4, a value of a storage capacitor Cst for keeping a voltage drop Vdrop within 80 mV (i.e., 1 gray voltage of 64 gray levels) can be given by the following equations:Vlc(t)=Vlc(0)[Exp(−Tf/RoffCt)](If Vdrop=Vlc(0)−Vp(t))  (1)wherein Vlc represents a liquid crystal driving voltage; Tf is one frame interval; Roff is an internal resistance; Vp is a pixel voltage; Vdrop is a voltage drop; and Ct is total capacitor value (i.e., liquid crystal capacitance, Clc+storage capacitor value Cst).Vdrop=Vlc(0)[1−Exp(−Tf/RoffCt)]  (2)wherein Vdrop represents a voltage drop; Tf is one frame interval; Vlc is a liquid crystal driving voltage; and Ct is total capacitor value.Ct>(Tf/Roff)/Ln[Vi/(Vi−Vdrop)]  (3)wherein Ln represents an inductance; and Vi is an initial voltage.
In equation (3), Ct=Clc+Cst; Tf=16.7 ms (1 frame interval); Vlc=5 V; Vdrop=80 mV; and Roff=Vi/Ioff=5 V/4 pA=1.25E+12 Ω.
Table 1 describes an area and an occupied ratio of the storage capacitor according to a resolution when a thickness of the gate insulating film 9 formed between the storage electrode 6 and the gate line 3 in a high-resolution LCD shown in FIG. 1 is 4000 Å.
TABLE 1Sub-PixelRequestedOccupiedsizeClcminimal CstStorage sizeratio300 PPI2.39E-093.4E-148.14E-135.49E-09230.0%250 PPI3.46E-095.5E-147.93E-135.35E-09154.8%200 PPI5.29E-099.3E-147.56E-135.10E-09 96.3%150 PPI9.53E-091.8E-136.64E-134.48E-09 47.0%100 PPI2.15E-094.5E-133.95E-132.67E-09 12.4%
It can be seen from Table 1 that, as a resolution increases, a ratio of an area occupied by the storage capacitor within a unit pixel increases. Also, the aperture ratio of the LCD is greatly reduced.
Table 2 compares a storage capacitor value and an aperture ratio of a high-resolution LCD with those of a ferroelectric liquid crystal display (FLCD) when a thickness of the gate insulating film 9 formed between the storage electrode 6 and the gate line 3 is 4000 Å.
TABLE 2200 PPIFLCD MODEL 1FLCD MODEL 2Sub-Pixel52922594725947Storage5992784.57113.7Aperture area241415373.511044.3Aperture ratio45.60%59.2%42.6%
As can be seen from Table 2,although a storage capacitor value of a ferroelectric liquid crystal display (FLCD) is three times larger than that of a conventional liquid crystal display panel, an aperture ratio of a FLCD is approximately 50% in comparison with that of a conventional liquid crystal display panel.